1. Field of the Invention
The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing a semiconductor device with group III-V channel and group IV source-drain. The method is to form a group III-V channel on a group IV substrate by epitaxy, or a group IV source-drain on a group III-V element structure by epitaxy.
2. Description of the Related Art
Generally, a metal-oxide-semiconductor field effect transistor (MOSFET) with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents, so the gate dielectrics is formed with a high-dielectric-constant dielectric material, instead of silicon dioxide, thereby reducing the gate leakage current. Herein, the high dielectric constant refers to a dielectric constant higher than 10.
However, since the high-dielectric-constant gate dielectric layer may not be compatible with polysilicon, it may desirable to use metal gate electrodes in devices that includes the high-dielectric-constant gate dielectric. When a CMOS device with metal gates is made, it may be necessary to make the NMOS and PMOS from different materials. A replacement gate process may be used to form gates from different materials. In the process, a first polysilicon layer, bracketed by a pair of spacers, is selectively removed as a second polysilicon layer to create a trench between the spaces. The trench is filled with a first metal. Then, the second polysilicon layer is removed and replaced with a second metal that differs from the first metal.
US Patent Application Publication No. 2006/0046399A1 disclosed a method for forming a replacement metal gate electrode. A dummy dielectric layer and a sacrificial layer are sequentially formed on a silicon substrate 10. The dummy dielectric layer and the sacrificial layer are patterned, and a shallow source drain region 14 is formed by ion implantation using the patterned sacrificial layer as a mask. Sidewall spacers 16 and 17 are sequentially formed on the opposite sides of the sacrificial layer. Ion implantation is performed once again to form a deep source drain region 12. A dielectric layer 20 is deposited on a resultant structure, and the dielectric layer 20 on the patterned sacrificial layer is removed by chemical mechanical polishing. The sacrificial layer is removed to form a hole that is positioned between the sidewall spacers 16 and 17. A sidewall spacer 24 is formed in the hole. The dummy dielectric layer is removed by wet etching. As shown in FIG. 1, the portion of the silicon substrate 10 to be functioned as a channel portion, which is exposed by the opening between the sidewall spacers 24, is etched by dry etching, to form a trench 26. As shown in FIG. 2, a part of the trench 26 is filled with an epitaxial material 28 such as silicon germanium, germanium, InSb, or carbon-doped silicon to the level of the upper surface of the shallow source drain region 14. As shown in FIG. 3, the sidewall spacer 24 is removed. A U-shaped high-dielectric-constant dielectric layer 32 is formed. An N-type metal layer 30 is formed on the dielectric layer 32.